Senior SerDes Micro Architect

Join our innovative Mixed-Signal Design group as a SerDes/PHY Micro Architect, and help shape the future of high-speed silicon for next-generation networking and GPU's ASICs. In this strategic role, you will define and refine system-level features and micro-architecture requirements for advanced SerDes and PHY IP, with a special focus on firmware (FW) architecture and CD architecture integration.

You will be involved end-to-end—from early requirements through pre-silicon architecture to post-silicon bring-up and customer-facing debug—collaborating closely with design, verification, firmware, hardware, and system teams. Your work will enable cutting-edge technologies such as CPO and NVLink.

What You’ll Be Doing

• Define system-level features and micro-architecture requirements for SerDes technology, bridging hardware and firmware domains.
• Align architecture definitions with both FW development and CD implementation flows, ensuring seamless integration across product stages.
• Translate system and customer requirements into scalable, actionable features for next-generation silicon.
• Drive and contribute to all silicon development phases: pre-silicon specification, hands-on lab bring-up, validation, debug, and customer support.
• Collaborate with cross-functional teams across ASIC design, verification, firmware, board engineering, and customer delivery.
• Lead or contribute to technical reviews, issue root-cause analysis, and architectural methodology improvements.
  
  

• BSc or MSc in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of experience in PHY/SerDes micro-architecture or high-speed silicon development.
• Strong background in high-speed interfaces (e.g., Ethernet, InfiniBand, NV Link).
• Proven ability to define system features and participate in hands-on bring-up and validation—spanning firmware and hardware domains.
• Experience with architecture requirements impacting both firmware flows and CD delivery needs.
• Strong analytical and problem-solving skills with excellent communication and collaboration capabilities.
• Knowledge of relevant interface and protocol standards (e.g., IEEE, PCIe).
• Expertise in defining and integrating SerDes architecture with firmware systems and delivery pipelines.
• Experience working closely with CD teams to ensure readiness for deployment, debug, and customer use cases.
  
  

• Hands-on experience using lab equipment for signal analysis and post-silicon debug.
• System-level understanding of architecture spanning RTL, firmware, and validation.
• Experience in RT FW development
• Contributions to breakthrough products leveraging cutting-edge silicon and SerDes technology.