Senior Chip Architect, Next Gen Networking

We are seeking a highly motivated Chip Architect to join our team and help shape the future of next-generation high-performance networking. NVIDIA’s next-generation Ethernet and NVL switches are at the core of the world’s most advanced compute clusters — from powering AI factories to scaling NVL-based GPU systems used in training/inferencing of the largest foundation models. As a Chip Architect at NVIDIA, you will play a central role in defining the architecture of these high-bandwidth, low-latency switches. Your work will directly impact how AI supercomputers, hyperscale data centers, and cutting-edge research platforms communicate at scale. You will join a team with a strong track record of first-in-the-world products and help deliver the next leap in networking technology.

What You'll Be Doing

• Define the end-to-end architecture and full feature set of next-generation NVL and Ethernet switch chips across all stages of the product lifecycle — from early concept to deployment.
• Develop architectural specifications and design guidelines, and drive trade-off analyses across multiple architecture options.
• Lead research and exploration of future architectures, including innovation that contributes to patent development.
• Collaborate closely with cross-functional teams — including other architecture groups, logic design, firmware, system software, and research — to ensure successful execution and integration.
• Act as a technical leader and subject matter expert, mentoring others and driving architectural excellence across the organization.
  
  

• BSc or MSc in Electrical Engineering, Computer Engineering, or related field
• 7+ years of proven experience in chip architecture, digital design, or design verification
• Solid understanding of digital ASIC design and strong familiarity with the full chip development cycle
• System-level thinking — ability to reason across hardware/software boundaries and understand how switch architecture impacts end-to-end performance
• Comfortable navigating between RTL, models, and system software to drive architectural clarity
  
  

• Deep knowledge of networking and compute systems
• Hands-on experience in system architecture across domains such as networking, CPUs, GPUs, or memory subsystems
• Background in in-network computing or data-path acceleration