Senior SerDes Logic u-Architect

Job Details

Job Description:

We are seeking a highly experienced SerDes Logic Micro-Architect to lead the design and development of high-performance SerDes IP blocks. In this role, you will define and implement RTL for complex logic, contribute to architectural decisions, and ensure seamless integration into SoC environments.

Key Responsibilities

• Define and develop RTL for SerDes IP blocks, including cell libraries, functional units, and subsystems.
• Collaborate on architecture and microarchitecture definition for high-speed serial interfaces.
• Optimize logic to meet power, performance, area (PPA), and timing goals, ensuring physical design integrity.
• Review and contribute to verification plans; debug and resolve RTL issues to ensure functional correctness.
• Support SoC teams in integrating and verifying SerDes IP, ensuring high-quality handoff and compliance.
• Drive quality assurance and contribute to post-silicon validation and debug efforts.
• Interface with communication standards and contribute to serial link optimization and firmware development.
  
  

• B.Sc. or M.Sc. in Electrical or Computer Engineering.
• 10+ years of industry experience delivering complex, high-performance IP through mass production.
• Deep expertise in SerDes and PHY design, including RTL and firmware development.
• Strong understanding of serial communication standards and link optimization techniques.
• Experience with post-silicon validation, debug, and design refinement.
• Familiarity with system architecture and digital signal processing (DSP) concepts is a plus.
• Excellent problem-solving skills and ability to work across cross-functional teams.