Senior RTL Design Engineer, Google Cloud

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience architecting networking ASICs from specification to production.
• Experience developing RTL for ASIC subsystems.
• Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
  
  

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
• Experience architecting networking switches, end points, and hardware offloads.
• Experience working with design networking like: RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability.
• Experience with Mastery of TCP, IP, Ethernet, PCIE, and DRAM, and familiarity with Network on Chip (NoC) principles and protocols (e.g., AXI, ACE, and CHI).
• Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
• Ability to adeptly estimate performance through analysis, modeling, and network simulation, and drive performance test plans.
  
  

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

You will also be responsible for performance analysis for a networking stack.

The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Lead an ASIC subsystem.
• Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
• Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
• Define efficient micro-architecture and block partitioning/interfaces and flows.
• Implement designs in SystemVerilog.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .