Senior RTL Design Engineer

Senior / Staff RTL Design Engineer

📍 Location: Haifa / Hod HaSharon, Israel | Full-time, On-site

Job Description:

We are looking for a highly skilled Senior or Staff RTL Design Engineer to join our advanced ASIC design team, focusing on microcontroller and application processor subsystems.

In this role, you will take end-to-end ownership of functional RTL blocks, from micro-architecture definition through to synthesis and timing closure. You will collaborate closely with architecture, verification, modeling, validation, and physical design teams to deliver cutting-edge silicon that meets strict performance, power, and area (PPA) goals.

Responsibilities:

• Define and develop RTL for complex micro-architecture components in SoC designs
• Collaborate with architecture and verification teams to ensure functional correctness and coverage
• Analyze synthesis and timing reports, identify bottlenecks and optimize for PPA
• Work on CPU/microcontroller subsystems, interconnects, memory controllers, and cache logic
• Support system integration and bring-up efforts
• Guide and mentor junior engineers as needed

Minimum Qualifications:

• B.Sc. in Electrical Engineering, Computer Engineering, or related field
• — and 6+ years of relevant ASIC/RTL design experience
• (or M.Sc. with 5+ years / Ph.D. with 4+ years)
• Strong hands-on experience in RTL design using Verilog
• Deep understanding of SoC architecture, microprocessors, memory systems, and bus protocols
• Experience with synthesis, timing analysis, and closing complex designs under PPA constraints
• Excellent collaboration and communication skills
• Willingness to work full-time on-site, 5 days a week

Preferred Qualifications:

• 10+ years of experience in RTL/ASIC design
• Familiarity with AMBA protocols such as AXI, ACE, or CHI
• Experience with cache coherence, low-power design techniques, and formal verification collaboration
• System-level understanding of operating systems, drivers, and firmware interfaces
• Exposure to industry-standard EDA tools (e.g., Synopsys, Cadence)