DFT Engineer

Job Details

Job Description:

We are looking for a skilled Design-for-Test (DFT) Engineer to join our silicon design team. In this role, you will be responsible for developing and integrating DFT logic into SoC designs, ensuring high test coverage, manufacturability, and product quality.

Key Responsibilities

• Design and implement DFT logic including SCAN, MBIST, BSCAN, and TAP at the block, subsystem, and SoC levels.
• Develop RTL and structural code to integrate DFT features, ensuring alignment with power, performance, area (PPA), and timing goals.
• Support DFT timing closure, test content generation, and delivery to manufacturing.
• Collaborate in defining architecture and microarchitecture features related to DFT, including in-system test and processor monitors.
• Generate and validate high-volume manufacturing (HVM) test content for rapid bring-up and production ramp on automatic test equipment (ATE).
• Optimize test logic to meet test coverage, DPM (defects per million), and test time/memory reduction targets.
• Review and contribute to verification plans; drive verification of DFT features to ensure functional correctness.
• Integrate DFT blocks into functional IP and SoC designs, supporting SoC teams to ensure seamless integration.
• Work closely with post-silicon and manufacturing teams to validate DFT features on silicon, support debug efforts, and document learnings for future improvements.
• Drive continuous improvement in DFT methodologies and test quality across product generations.
  
  

• B.Sc. or M.Sc. in Electrical or Computer Engineering.
• 5+ years of experience in DFT for SoC or ASIC designs.
• Strong knowledge of SCAN, optional MBIST, BSCAN, and JTAG.
• Proficient in Verilog/SystemVerilog and DFT tools (e.g., Synopsys, Mentor (Simense), Tessent).
• Experience with DFT timing closure, test pattern generation and verification, optional ATE bring-up.
• Solid scripting skills at TCL.
• Excellent problem-solving and teamwork abilities.