DFT Technical Lead - Digital IC Design

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell’s DCE (Data Cloud Engineering) is a global design team at the forefront of developing cutting-edge silicon products that power the most advanced applications and technologies in the semiconductor industry.

Being part of our team means pushing boundaries, exploring the unknown, and building deep technical expertise—while making a real difference.

We are excited to offer an excellent opportunity to join our Israel-based Switch SoC department as a DFT (Design for Test) Team Leader. Our global Switch DFT group is responsible for the architecture, design implementation, validation, and execution of end-to-end testability strategies and DFT solutions for current and next-generation products that drive the future of data communication in a hyper-connected world of cloud and AI.

What You Can Expect

• Technically lead and be a part of a highly experienced DFT team developing best-in-class, high-complexity products.
• Develop and improve DFT tools methodologies, focusing on quality, customer needs, and continuous improvements of the team processes.
• Work closely with Architecture, Design, Implementation and OPS teams to understand the implementation and come up with proper DFT/Validation strategy
• Lead the complete DFT project activities, own the validation of the DFT logic, and provide patterns to the Product Engineering team.
• Own the DFT sign-off to ensure bug-free design and high ATPG and MBIST coverage for the product.
• Work with the post-silicon teams on debug support and to help root-cause any failures.
• Lead direct and indirect reports by setting goals, planning the tasks, and technical coaching.
  
  

• B.E./B.Tech. or M.E./M.Tech. in electrical engineering with 7-12+ years of experience in DFT.
• Excellent design and debug skills for RTL/GL-based simulations and the ability to debug issues on Si.
• Proven hands-on experience and deep understanding of MBIST, scan insertion, and ATPG, including pre-Si design stages and post-Si bring-up and product qualification support.
• Solid knowledge of standard DFT EDA tools (Mentor, SNPS) for memory BIST, ATPG, and boundary scan. Strong advantage if familiar with Tessent/Mentor DFT tools and methodologies.
• Solid understanding of JTAG standards and their usage for DFT.
• Understanding and experience with timing closure and PD-related aspects of VLSI flow and DFT sign-off.
• Proven leadership and problem-solving skills focusing on uncompromised quality, innovation, and continuous learning and improvement.
• Strong communication, collaboration, and teamwork skills and ability to work in a global team environment.
• Ability to build plans, define immediate and future needs based on project requirements, and track execution.
• Experience in direct management of multidisciplinary teams, including DFT, design, verification, validation, etc.—advantage.