CPU Design for Test Engineer, Google Cloud

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• 2 years of experience in Automatic Test Pattern Generation (ATPG) methods.
• Experience with multiple projects in Design for Testing (DFT) scan design and verification.
• Experience with Design for Testing (DFT) techniques and tools, Application-Specific Integrated Circuit (ASIC) Design for Testing synthesis, simulation, and verification flow.
  
  

Preferred qualifications:

• Master's degree in Electrical Engineering.
• Experience working with Automated Test Equipment (ATE) engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
• Experience in System on a chip (SoC) cycles, including silicon bringup and silicon debug activities.
• Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
• Experience in fault modeling.
  
  

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will play a crucial role in Design for Testing (DFT), and support devices to production. You will be responsible for developing flows, automation, and methodology, executing DFT activities. You will be responsible for testing vectors end to end, from generating DFT content, debugging to coverage goals, simulating it at gate level, sign-off DFT to tapeout, and debugging results.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
• Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
• Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements.
• Perform scan verification at Register-Transfer Level (RTL) and gate level.
• Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .