CPU Design Integration Engineer, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
• Experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language.
• Scripting experience.
  
  

Preferred qualifications:

• Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
• Experience with chip design flow, physical design, IP integration, and Design for Testing (DFT).
• Ability to muti-task, and have a can-do approach.
• Excellent communication and facilitation skills.
  
  

About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Define and implement solutions for complex design, integration and verification problems using in house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
• Be involved in project development and convergence with the highest quality, work on issues as they arise through design and implementation.
• Connect between RTL design, physical design, DFT, external IPs and System on a Chip (SoC) while maintaining project priorities.
• Maintain project infrastructure and stability.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .