VLSI DFT Manager

For an exciting well-funded start-up, we are seeking a talented and experienced VLSI DFT Manager to build, lead and shape the Design-for-Testability (DFT) strategy for our next-generation ASICs and SoCs. In this leadership role, you will oversee the full DFT lifecycle, from specification and architecture to silicon bring-up and validation. You will work closely with cross-functional teams, including backend, verification, analog, and software engineering, ensuring seamless integration of DFT methodologies into the design flow

Requirements:

Responsibilities:

• Build, Lead and manage a team of DFT engineers, shaping the team’s growth and capabilities as you drive the development of DFT strategies for complex SoCs.
• Define and implement DFT architecture, including boundary scan, scan chains, DFT compression, Logic BIST, TAP controller, clock control blocks, and MBIST logic.
• Collaborate with IP vendors and internal teams to integrate DFT-related IPs such as memories, test controllers, TAP, and MBIST.
• Lead DFT analysis and fault modeling, ensuring comprehensive test coverage and yield optimization.
• Manage silicon bring-up and validation, debug ATPG patterns, compressed ATPG patterns, MBIST, and JTAG-related issues on ATE.
• Define and implement test plans for analog IPs and develop special analog test strategies.
• Ensure high test quality by addressing Design Rule Checks (DRCs) and applying necessary design fixes.
• Work closely with cross-functional teams (backend, verification, analog, software) to ensure DFT integration into the overall SoC design flow.
• Document DFT architecture, including test sequences, boot-up sequences, and test pin configurations.
• Drive continuous improvement by staying up-to-date with industry trends and best practices in DFT and test methodologies.
  
  

• 8+ years of experience in DFT specification, architecture, insertion, and analysis for complex ASICs/SoCs.
• 3+ years of team leadership experience, with a proven track record of managing DFT engineers and delivering successful projects.
• Hands-on experience in silicon bring-up, debug, and validation of DFT features on ATE.
• Expertise in ATPG, MBIST, JTAG, fault modeling, and testability techniques.
• Proficiency with EDA Test tools, such as Design Compiler, Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress.
• Strong knowledge of ASIC DFT, synthesis, simulation, and verification flows.
• Excellent problem-solving, debugging, and organizational skills.
  
  

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with Analog IP integration.
• Familiarity with high-speed interfaces and mixed-signal DFT methodologies.
• Proven experience in the full design cycle, including synthesis, implementation, and testing of DFT methodologies.