Senior Signal Integrity Engineer

Description

Senior Signal Integrity Engineer

Location: Raanana

About Us

DriveNets is at the forefront of developing innovative solutions in high-speed electronics. Our cutting-edge technology serves the next generation of networking and communications, including Ethernet routers and high-performance platforms for the most demanding applications. We are committed to solving complex challenges and pushing the boundaries of what's possible in signal and power integrity.

The Role

We are looking for an experienced Senior Signal Integrity Engineer to join our Hardware Engineering team. This role focuses on ensuring optimal signal integrity for high-speed interfaces, including Ethernet, PCIe, DDR5, and other next-generation technologies. As part of the team, you will be responsible for performing signal integrity analysis, developing signal integrity models, and ensuring electrical compliance for high-speed SERDES I/Os.

Responsibilities

• Conduct signal integrity analysis and simulations for high-speed interfaces such as 112Gbps Ethernet, PCIe Gen5, and DDR5 interfaces.
• Develop and implement signal integrity guidelines for PCB design, ensuring high-performance and low-loss signal paths.
• Analyze and resolve signal integrity issues related to high-speed interfaces, including reflection, crosstalk, and power delivery network (PDN) issues.
• Collaborate with PCB layout engineers to optimize design for signal integrity, ensuring compliance with electrical standards and high-speed design best practices.
• Perform time-domain and frequency-domain analysis, including loss, jitter, and eye-diagram analysis.
• Utilize EDA tools such as Ansys SIWAVE, HFSS, or similar for simulation and validation of signal integrity designs.
• Work closely with cross-functional teams to integrate signal integrity considerations into the overall hardware design process.
• Develop behavioural models based on measured signal integrity data to inform future design and simulation work.
• Conduct pre- and post-layout simulations and measurements for high-speed signal interfaces.
  
  

• Bachelor's or Master’s degree in Electrical/Electronics Engineering with 10+ years of relevant experience.
• Strong understanding of electromagnetic (EM) concepts and transmission line theory.
• Extensive experience in signal integrity analysis for high-speed serial interfaces, including Ethernet, PCIe, and DDR5.
• Proficiency in using EDA tools like Ansys SIWAVE, HFSS, or similar.
• Hands-on expertise in time-domain and frequency-domain analysis, jitter, loss, and eye-diagram analysis.
• Strong background in HSPICE simulations and model development.
• Experience with PCB layout techniques for high-speed designs.
• Excellent communication skills and the ability to work effectively in a collaborative team environment.
  
  

• Experience with advanced simulation tools and techniques.
• Experience with high-speed interfaces such as 112Gbps PAM4 Ethernet, PCIe Gen5, and DDR5.
• In-depth knowledge of high-speed PCB design and layout principles.
• Familiarity with power integrity and power noise simulations.