Junior Physical Design Engineer

The Mobileye EyeC VLSI team designs chips for RADAR systems used in ADAS and autonomous vehicles. Our Physical Design team operates in a startup-like environment, emphasizing technical expertise, execution, and ownership. Each engineer in the Physical Design team takes full responsibility for their work, from initial definition through execution and final sign-offs. Engineers collaborate closely with design and architecture teams to develop constraints, conduct design reviews, and implement RTL modifications to ensure convergence.

We are seeking a Junior Physical Design Engineer. In this role, you will play a key part in the design of state-of-the-art SoCs, from definition to Tape-Out.

What will your job look like:

• Hands-on physical design block owner from RTL to GDS.
• Floorplan exploration with guidance and collaboration with front-end and architecture teams.
• STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
• Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
• Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
• Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
  
  

• BSc or MSc degree in Computer Engineering or Electrical Engineering.
• Experience in scripting languages like Tcl/python/Perl/tcsh.
• Team player with excellent communication skills, customer orientation, and a “can-do” attitude.
• Experience in relevant domains - Advantage.