Senior Physical Design Power Optimization Engineer

NVIDIA is looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What You Will Be Doing

• Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
• Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
• Take part in project definition towards POR for optimized power, close interaction with BE team, FE, ARCH.
• Develop methodologies across the organization for BE related pre-to-post correlation.
  
  

• B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
• 10+ overall years of experience in physical design and/or BE power optimization aspects.
• Proven experience in RTL2GDS flows and methodologies.
• Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
• FE design experience is an advantage.
• Post Si experience is an advantage.
• Excellent problem-solving, partnership, and interpersonal skills.