DFT Design Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Marvell NSX Business Unit's DFT/DFx team is a critical part of our innovation in semiconductor technology, focusing on ensuring the reliability and testability of our advanced networking solutions. Our team is dedicated to developing and implementing cutting-edge DFT methodologies that enhance the quality and performance of our products.

What You Can Expect

• Design and implement advanced DFT architectures to ensure comprehensive testability in complex ASIC/VLSI designs.
• Develop and optimize test methodologies such as JTAG, SCAN, MBIST, and Boundary Scan (BScan) for maximum efficiency.
• Collaborate with cross-functional teams including RTL design, verification, backend, and post-silicon teams to ensure seamless integration.
• Conduct structural and functional verification of DFT features using industry-leading EDA tools (e.g., Cadence, Synopsys, Siemens (Mentor Graphics) .
• Perform post-silicon validation and debugging, analyzing silicon test results to refine DFT strategies for production.
• Enhance automation and workflow efficiency by implementing advanced DFT methodologies and integration tools.
• Support low-power design techniques, ensuring efficient DFT integration for power-sensitive applications.
  
  

• 6+ years of proven experience in ASIC/VLSI DFT design and verification.
• Bachelor’s degree in computer science, Electrical Engineering, or related fields.
• Extensive hands-on experience with EDA tools (e.g., Cadence, Synopsys, Siemens (Mentor Graphics).
• Deep understanding of DFT methodologies, including JTAG, SCAN, MBIST, and BScan.
• Strong debugging skills to identify and resolve design and test issues.
• Experience with Spyglass Lint, CDC and RDC (advantage).
• Familiarity with I/O and package design principles (advantage).
• Experience with low-power design techniques and methodologies (advantage).
• Excellent analytical and problem-solving skills, with the ability to work independently and manage multiple tasks.