Senior Design Verification Engineer

At Wiliot, we bring connectivity and intelligence to everyday products and packaging; things previously disconnect from the Internet of Things. The Wiliot Platform combines cloud services and IoT Pixels, computing elements that can power themselves by harvesting radiofrequency energy. This revolutionary mixture of cloud and semiconductor technology is being used by some of the world’s largest brands, food, and pharmaceutical companies to change how we make, distribute, sell, use and recycle products. Our investors include Amazon, Verizon, NTT DoCoMo, Qualcomm, PepsiCo, and Softbank Vision Fund 2. Join us and help pave the way for the new IoT.

Wiliot is looking for a talented, experienced and highly motivated engineer to take part in the verification efforts for the company’s core product. This position involves building and maintaining a complex verification environment, defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.

In Addition, it involves day to day work with other groups within the company such as System, Software, Analog, DFT and lab activity according to requirements.

Responsibilities:

• Define, architect and develop verification environments and test benches, using System Verilog and UVM methodology
• Build and maintain an agile verification environment that ties into various systems (MATLAB, SW stack, FPGA, HW/SW Co-simulation and Verilog-HDL)
• Review specifications and develop attributes, tests, and coverage plans
• Create test plans, plan tasks, execute, track and reach verification closure
• Work closely with Design, Software, Analog and System teams to understand the functional, power and performance goals of the product and ensure its quality
• Define and develop block-level verification environments, to be integrated and reused in full-chip environments
• Define methodologies and verification flows
• Maintain Linux environment and release flow involving several R&D groups, including version control (GIT) and internal developed tools
  
  

• Bachelor’s or Master’s degree in Electrical Engineering/Computer Engineering/Computer Science, or an equivalent experience
• 5+ years of experience in design verification, preferably in System Verilog/UVM
• Knowledge of digital ASIC design flows
• Knowledge of SoC development work methodologies and tools
• Knowledge of industry-standard tools, including Verilog, Verilog simulators and debug tools
• Experience in Unix/Linux environment, Make and scripting languages such as Python/C-Shell/Bash/tcsh/perl
• Version control (GIT - advantage)
• Knowledge of assertions, preferably SVA (Formal Verification experience - advantage)
• Experience in verification of SoC or full chip level - advantage
• Experience in FPGA verification - advantage
• Experience with VIPs - advantage
  
  

• Strong analytical and problem-solving skills
• Out-of-the-box thinker, go-getter that welcomes new environments and challenges
• Team Player with excellent interpersonal skills
• Motivated, able to coach and mentor other team members