Physical Design Senior Staff Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Switching Physical Engineering Place & Route team involves significantly in developing Marvell NSX products, from the early stages of floor planning through physical integration of Place, Route, Power, Physical Verification, Analog connectivity and Chip IO interface towards package and system, beside preparing Tape-out database for fabrication.

Marvell’s custom solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance chips in a leading-edge CMOS process technology, targeted at server datacenter and networking applications.

What You Can Expect

• Designing for advanced process nodes (3nm and 2nm).
• The candidate will join a team of experts Layout engineers, developing Marvell Switches devices Layout till Tape-out.
• Our team is looking for an experienced Place & Route team member for implementing our advanced networking devices for datacenter market.
• As a member you will be challenged with complex physical integrations and verification. In addition, you will work collaboratively with expert interfaces such as: Design, Full-Chip timing, Signal integrity, Package and Circuit Design.
  
  

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields.
• At least 5 years of experience in Place & Route, manual and automatic layout implementations.
• Rich familiarity with EDA Place & Route tools as Innovus or ICC2.
• Ability to implement complex modules and Top hierarchies from Netlist to GDS, including all stages from Floorplan till Tape-out.
• Deep practical knowledge in physical verification for sign-off quality in advanced processes as 5nm and newer.
• TCL scripting capabilities is an advantage.