Senior System/FW Validation Engineer

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

Job Description

The mission of this role is to perform system validation for Astera Lab’s highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more.

You will be part of the site located at Israel (Haifa – Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey at Astera Labs Israel.

Basic Qualifications

• Strong academic and technical background in electrical or computer engineering
• ≥3 years’ experience validating and/or developing complex SoC/silicon products for Networking and/or Server & Storage applications
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!
  
  

• Hands-on, thorough knowledge of high-speed protocols like Ethernet CXL, PCIe, NVMe,.
• Silicon/System bring-up, validation, and debug experience, including customer’s systems.
• A Python coding experience
• Familiarity with validation techniques C, C++
• Experience with lab equipment as protocol analyzers, chambers, in-circuit debuggers, and CPU-based tool suites.
• Familiarity with lab testing automation techniques
  
  

• Familiarity with devices trees and related debugging techniques.
• Familiarity with board system design
• C\C++ for embedded FW and device drivers
• Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence
• Familiarity with CXL compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.
• Experience working with DRAM memory vendors on DDR4 or DDR5 to identify issues and working on SoC HW/FW to improve memory calibration and tuning sequences.
• Knowledge of memory subsystem compliance from a data integrity and RAS is a plus.
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.