VLSI Physical Synthesis Engineer

About Us

NeoLogic is a unique fabless semiconductors startup; We develop processors to address the ever-increasing workloads of next generation AI data centers.

Role Description

We are looking for a physical synthesis engineer to join our fast-growing team. The ideal candidate would have hands-on experience of RTL-to-Netlist flows including: Physical Synthesis, Formal Verification, Floor-planning, and STA.

Qualification, skills and knowledge requirements:​

• B.Sc. in Electrical Engineering, Computer Engineering, or related field
• At least 5 years of relevant hands-on experience
• Experience in physical synthesis of designs with at least 2M instances
• Experience using Synopsys Design Compiler or Cadence Genus tools
• Experience in Formal Verification - advantage
• Experience in Timing and Power analysis - advantage