Junior Verification Engineer

We're looking for a talented Junior Verification Engineer!

What will you do

• ?Responsible for the full life cycle of verification - from verification planning to test execution, to collecting and closing coverage
• .Plan the verification of complex digital blocks, containing embedded processors, by fully understanding the design specification and interacting with design & SW engineers to identify important verification scenarios
• .Create an automated constrained-random verification environment using SystemVerilog & scripting languages
• .Identify and write all types of coverage measures for stimulus and corner-cases
• .Debug tests with design engineers to deliver functionally correct design blocks
• .Collaborate closely with design and verification engineers in active projects and perform hands-on verification
• .Close coverage measures to identify verification holes and to show progress towards tape-out

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Requirement

• s:BSc. in Electronic Engineeri
• ngAt least 1 year experience as verification engine
• erKnowledge in verification methodologies, tools (simulators , coverage tools, assertions , formal, etc.) and techniqu
• esBroad Knowledge in SystemVerilog & Veril
• ogGood knowledge of Unix environment and script languages : Python , Tcl , C Shell , Pe
• rlMethodological approach to building of verification environment and test pl
• anMethodological approach to the verification tasks planning and executi