VLSI Backend Design Manager

About Us

NeoLogic is a unique fabless semiconductors startup. We develop disruptive technology known as "Quasi-CMOS", to address the ever-increasing workloads of video, artificial intelligence, machine learning, data analytics, and more, in the cloud and at the edge.

Our processors will outperform any CMOS implemented CPU in terms of PPA at any process node. Ready for your next challenge? come join our growing team of talents!

Role Description

We are looking for an experienced physical backend design manager to join our fast-growing team. The ideal candidate would have hands-on experience of the full ASIC backend flow from RTL to GDS: Synthesis, Formal Verification, Floor-planning, PnR, STA and Physical Verification (DRC / LVS).

What you will be doing

Build and manage an RTL2GDS design team for implementing NeoLogic's next-gen processor using our innovative technology. Your ultimate goal will be to enhance performance per power and area across various targeted workloads.

Qualifications

• B.Sc. in Electrical Engineering, Computer Engineering or related field.
• At least 10 years of proven experience of backend implementation of SoC.
• At least 4 years of experience as a team leader.
• Experience with place & route tools and flows (Synopsys / Cadence).
• Experience and understanding of static timing analysis.
• Extensive know-how in floor-planning, power grid distribution and analysis.
• Experience with advanced CMOS process nodes (5nm/3nm) - advantage
• Experience with integration of mixed-signal IPs and I/O integration - advantage
• Extensive understanding of DRC / LVS - advantage
• Knowledge in Verilog, DFT design – advantage