Design Verification Engineer

Job description

Company Description

Elbit Systems Ltd. is an international technology company that specializes in defense, homeland security, and commercial programs worldwide. The company operates in aerospace, land, and naval systems, C4ISR, unmanned aircraft systems, advanced electro-optics, EW suites, signal intelligence systems, data links and communications systems, radios and cyber-based systems, and munitions. Elbit Systems develops new technologies for defense, homeland security, and commercial applications.

Role Description

We are seeking a Verification Engineer to join our dynamic team, specializing in System Verilog and UVM methodology. You will be responsible for designing and implementing verification plans, utilizing UVM to ensure comprehensive coverage and efficiency. Plan the verification of complex digital design by fully understanding the design specification and the implemented algorithms. You will collaborate with cross-functional teams to identify and resolve design issues, and contribute to the continuous improvement of our verification processes. Working closely with architecture, design and algorithm teams to identify important verification scenarios. Your contributions will have a direct impact on our vital defense capabilities.

Key Responsibilities:

1. Responsible for the entire Verification cycle, from initial requirements gathering to achieving full coverage. Steps will include developing a detailed Test Plan, creating and optimizing the UVM environment, implementing comprehensive Coverage strategies, and integrating a Scoreboard for effective verification and validation.

2. Collaborate closely with a multidisciplinary team of engineers to ensure our FPGA solutions align with the stringent requirements of our high-performance end products.

3. Adapt to evolving project needs, demonstrating flexibility and innovation in your approach.

Skills and Qualifications:

1. Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.

2. 4+ years of experience with UVM methodology and System Verilog

3. Experience with RTL debugging from Block level to System Level

4. Experience with Questa Simulator - advantage

5. VHDL/Verilog proficiency – advantage

6. TCL/Python/bash experience – advantage

7. Linux/NC experience – advantage