Physical Design Senior Staff Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Backend Group is a global group responsible for the Physical Design and implementation of switching chips done in the Switching BU. Our job is to tape out chips on time while meeting the target speed, area, and power. The group emphasizes quality and uses cutting-edge technologies on some of the largest, most complex chips in the industry.

What You Can Expect

• The candidate will be responsible for flow structuring and managing large, complex blocks with a focus on timing closure for high-speed clocks, challenging floorplans, and oower and area optimization.
• Implement the design from Synthesis to GDSII, including synthesis, scan insertion, P&R, timing sign-off, and physical sign-off.
• Perform comprehensive checks to achieve higher Quality of Results (QoR) and optimize power based on power analysis results.
• Develop and refine methodologies to improve workflow efficiency.
• Collaborate with designers to address RTL issues related to backend timing closure and congestion resolution.
• Debug and enhance the flow to drive advancements in backend processes.
  
  

• Bachelor’s degree in Electrical/Computer Engineering, Computer Science, or related fields.
• 5-15 years of experience in full backend activities.
• Strong understanding of Place and Route (PnR) and Synthesis (Synt) with experience handling complex blocks using the latest technology nodes, such as 7nm, 5nm, and 3nm.
• Exposure to multiple tools across Cadence and Synopsys platforms.
• Strong Static Timing Analysis (STA) knowledge and work experience is essential, with full-chip STA exposure considered an advantage.
• Experience as a Blocks (RTL2GDS) or full-chip timing engineer with expertise in advanced process nodes (12nm, 5nm, and 3nm).