Senior Physical Design Engineer

At NextSilicon, we are reimagining high-performance computing. Our pioneering coprocessor vastly accelerates supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

NextSilicon is looking for a talented and experienced engineer to participate in the physical design of the company’s product. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the company’s design efforts and will have a significant influence on product architecture.

Requirements:

• 7+ years of physical design experience, leading complex process designs
• In-depth knowledge of process and circuit design
• Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, CTS, place and route
• Experience developing and implementing power-grid and clock specifications
• Good command of industry-standard physical design and synthesis tools
• Understanding of scripting languages, such as Perl and Tcl
• Working knowledge of extraction and STA methodologies and tools
• Good understanding of physical design verification methodology for debugging LVS and DRC issues at chip and block level
• Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power
• Leading projects and managing small groups: advantage
  
  

• Generate and analyze critical block- and chip-level static timing constraints
• Spec and define full chip floor plan, including pin placement, partitions, and power grid
• Develop and validate high-performance, low-power clock network guidelines
• Perform critical block-level place and route and create designs that meet timing, area, and power constraints
• Review the vendors’ physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
• Work with vendors on defining physical design methodologies and assist in flow development for chip integration