Physical Design Engineer

Samsung R&D Center is looking for Physical Design Engineer to join our Digital Design team.

Samsung (SIRC), shaping the world of tomorrow, Today. Focusing beyond the horizon and pushing exciting developments in many key areas of technology.

Samsung is creating a new era of continuous innovation, bringing value and contribution to society and creating a workplace where our employees can enjoy making the most of their talent, creativity and passion.

The Group

Developing sensors for world-wide markets. Our cameras are in the majority of premium mobile smart phones. We are involved in all development stages- from planning up to production.

We are looking for people with a broad set of technical skills, who are ready to tackle some of technology’s greatest challenges, who have the ability to think out of the box and bring the disruptive technologies that will define our future.

What will you do?

• Work as part of Digital Design team for design optimization prior to physical implementation.
• Define the Clock & Reset architecture with Architecture and Design team.
• Define and implement the Floorplan, SDC & UPF of Complex Sensor Chips with several Clock and Power domains.
• Work with different Samsung teams and 3rd party companies and guide them during full RTL to GDS flow towards signoff and Tape-out.
• Explore, develop and optimize FE and BE flow.
• Collaborate with other team members, including Software, Algorithms and Verification.

Requirements

• BSc in Electronic Engineering, MSc. an advantage
• At least 3 years of experience as a Backend Engineer
• Vast knowledge in full RTL to GDS
• Experience with floor-planning and power-grid planning
• Experience with synthesis, formal equivalence and STA.
• Capable of taking responsibility for various VLSI tasks and bringing them to successful implementation.
• Capable to manage communication I/F with external development teams.

Advantages:

• Experience as a technical leader.
• Experience on logic design.
• Experience on DFT (Scan/BIST), Physical verification and DFM