Senior Design Verification Engineer

BSC. in Electrical Engineering/ Computer Science

Experience of 5 years with verification techniques and the full verification life cycle of at least 2 chips

Experience in developing test benches and verification environments from scratch

Excellent knowledge and hands on experience of UVM

Experience with complex designs and advanced debug skills ability

Excellent presentation and interpersonal skills with a demonstrated ability to communicate complex technical concepts

Scripting skills in Python/ Perl/ TCL

“Nice to have” Skills and Experience

Experience in wider verification technologies such as formal property based verification

Experience with Palladium emulation platform

Familiarity with Cadence EDA tools such as Xcelium and Verisium