Staff Engineer, Physical Design

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

What You Can Expect

In this hybrid role based in LOCATION, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

What We're Looking For

To be successful in this role, you must Have :

• A bachelor’s degree in electrical/Computer Engineering, Computer Science, or related fields
• 1-3 years of related professional experience OR a master’s degree and/or PhD in Electrical/Computer Engineering, Computer Science, or related fields.
• Digital logic course and worked on projects that involved circuit design, testing, and timing analysis. - Have work or course experience where you created and tested a logic block and were able to look at the quality of results to ID improvements.
• Know formulas for timing analysis and concepts for synthesis, place, and route.
• Enjoy learning by doing the work and accessing guides and a mentor.
• Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before.