VLSI Circuit Layout

VLSI Circuit Layout

Job description

Analog / Digital circuit layout design on transistor level of RAAAM’s next-generation embedded memories in advanced CMOS technologies.

Responsibilities

• Memory bit cell layout and high-density optimization.
• Digital and Analog circuit layout in advanced process nodes (e.g. 16nm, 5nm, and below).
• Extraction (QRC) and layout optimization for reduced parasitic components.
• Working with circuit/architecture design teams to meet design criteria.

Qualifications

• 5+ years of experience with full-custom circuit design (e.g. 16nm, 5nm, and below). 
• Experience in the layout of SRAM blocks and standard cells.
• Experience with Cadence EDA (Virtuoso/Composer/Layout).
• Advantage: Skill knowledge.

Location

• Switzerland, Israel, Remote

Full / Part Time

• Full time

Skills

• VLSI circuit design, Cadence EDA tools (virtuoso/composer/layout), SRAM circuit design, Linux environment scripting

Screening Questions

1. How many years of work experience do you have with Analog Circuit Design?
2. How many years of work experience do you have in FinFET process nodes?
3. How many years of work experience do you have with SRAM?
4. How many years of work experience do you have with scripting (e.g., Python)?