Validation Engineer

Additional details:

R&D Center is looking for Digital Verification Engineer to join our team.

The company, shaping the world of tomorrow, Today. Focusing beyond the horizon and pushing exciting developments in many key areas of technology. Samsung is creating a new era of continuous innovation, bringing value and contribution to society and creating a workplace where our employees can enjoy making the most of their talent, creativity and passion. 

The Group

The Advanced Sensor Technology & SW IP team developing cutting edge solutions for Multi-Camera systems, utilizing advanced sensors products like ToF (Time of Flight) Sensor and DVS (Dynamic Vision Sensor).

We are looking for people with a broad set of technical skills, who are ready to tackle some of technology’s greatest challenges, who have the ability to think out of the box and bring the disruptive technologies that will define our future. 

What will you do?

• Responsible for the full life cycle of verification - from verification planning to test execution, to collecting and closing coverage.
• Plan the verification of complex digital blocks, containing embedded processors, by fully understanding the design specification and interacting with design & SW engineers to identify important verification scenarios.
• Create an automated constrained-random verification environment using SystemVerilog & scripting languages.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Collaborate closely with design and verification engineers in active projects and perform hands-on verification.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

• At least 3 years’ experience as verification engineer, completing at least 2 full development cycles
• Knowledge in verification methodologies, tools (simulators , coverage tools, assertions , formal, etc.) and techniques
• Broad Knowledge in System Verilog & Verilog
• Good knowledge of Unix environment and script languages : Python , Tcl , C Shell , Perl
• Methodological approach to building of verification environment and test plan
• Methodological approach to the verification tasks planning and execution

Advantage

• Experience with embedded processor verification.
• Ability to work well in a team