Senior Architect - Deep Learning Engineer

Description:

Samsung Israel Research Center (SIRC) is shaping the world of tomorrow, today. Focusing beyond the horizon and pushing exciting developments in many key areas of technology. Samsung is creating a new era of continuous innovation, bringing value and contribution to society and creating a workplace where our employees can enjoy making the most of their talent, creativity and passion. 

The team:

Join our team building next-generation platforms for Deep Learning accelerators. We seek an experienced architect to drive system-level performance optimization and hardware-software co-design, bridging algorithmic innovation with silicon implementation.

Key Responsibilities

• Define accelerator architecture (compute units, memory hierarchies, dataflow) optimized for ML inference workloads.
• Lead performance analysis using roofline models and analytical profiling to identify bottlenecks and optimization opportunities.
• Drive Design Space Exploration (DSE) and multi-objective optimization to navigate architectural trade-offs and identify optimal configurations under PPA constraints.
• Drive HW/SW co-design; specify hardware features and dataflow patterns that maximize compiler efficiency.
• Collaborate with Algorithm Research to map emerging models (LLMs, GenAI) onto hardware capabilities and identify acceleration opportunities.
• Develop pre-silicon performance models to validate architecture decisions.

• 7+ years in processor/AI accelerator architecture, HPC, or performance engineering.
• Demonstrated expertise in performance optimization methodologies, including roofline analysis, workload characterization, and Design Space Exploration.
• Experience with agentic workflows and autonomous optimization systems.
• Deep understanding of computer architecture, memory systems, and parallel processing.
• B.Sc. in Computer Engineering, Computer Science, or Electrical Engineering;

Advantages

• M.Sc. or PhD
• Experience with Black Box Optimization (BBO) and Hyperparameter Optimization (HPO).
• Track record in HW/SW co-design for AI accelerators.
• Experience with compiler architecture or MLIR.
• Publications or patents in computer architecture or ML systems.

*Applicants are asked to take special care to avoid sharing, using, or disclosing any trade secrets or confidential information belonging to their current or former employers, from the time they apply and throughout the entire recruitment process.