Verification Team Leader (1233)

RAD is a global leader for telecom access solutions. As an industry pioneer for over 40 years, RAD reliably supplies communications service providers and critical infrastructure operators in over 150 countries with best-of-breed EADs/NIDs, industrial IoT, 5G xHaul, and Operational WAN solutions. RAD co-innovates networking solutions with customers, offering always-on connectivity from anywhere, along with data-driven, AI-powered actionable insights at a glance.

Why choose RAD?

Our hybrid work model offers flexibility and work-life balance, while still maintaining a stable and growing company culture. At RAD, we value togetherness and prioritize building a strong team, which fosters a collaborative and supportive work environment.

Our commitment to professional development means we are focused on helping our team members continuously learning and growing in their careers. In addition, our impact-driven approach ensures that our employees are making a difference.

We are looking for a Verification Team Leader to RAD’s FPGA/ASIC R&D Group.

The FPGA/ASIC group is responsible for the next generation of network interface devices at a new level of complexity, as well as for developing advanced products for our customers.

The role can be preformed both in Ramat Hachayal - Tel Aviv or Beer Sheva site.

Roles and Responsibilities:

• Opportunity to participate in the development of RAD’s next generation product line, and to know some of the leading technologies in the field of communications (network processors).
• Participation in all stages of development, from verification programs and strategies, through
• Bachelor's degree in Computer Science/Electrical Engineering - mandatory
• 5 years of experience in defining and implementing verification environments in Specman/eRM or SystemVerilog/UVM environments
• Good communication skills and teamwork - mandatory
• Proven experience in a managerial position - advantage
• Experience with scripts (Python or Bash), SOC environments, formal verification, Palladium, gate level simulations - advantage.