Small Signal Array memory designer

Job Description

Develops and supports high speed custom memory HIPs for next Intel client and Server products. The team is part of “special circuit department” and acts as "SRAM Center of execution".

SRAM COE team is responsible to develop and support SRAM shared library, design and verification methodology , working closely with Intel "Advanced Design" group , post and pre silicon teams.

In addition, team responsible for execution and development of SRAM IP blocks to SOC partitions.

SRAM memories are the biggest memory blocks used on CPU chip.

Each memory block requires close work with architecture team to reach best area utilization, lowest power and required frequency.

Qualifications

• 3 years of proven experience in Memory \ Circuit \ Analog design experience
• Experience with: Virtuoso, Dynamic Simulations
• Knowledge of Timing characterization of IP – advantage
• Post silicone experience – advantage
• BS.C\MS.C in Electric Engineering
  
  

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.