Payload System Engineer

Define and manage complex, multidisciplinary system requirements for internal R&D teams and subcontractors.
Define the multi-ASIC payload architecture, including cross-silicon chip communication, interfaces, and high-speed SerDes links.
Define the full communication protocol-level architecture, split into different domains (DFE, HW, SW, FW, etc.), including MAC layer adjustments and high-speed data flows.
Define array synchronization, coherency, and clocking accuracy across vast arrays and between different ASIC components.
Lead the beamformer ASIC architecture definition and design reviews, from specification through silicon integration.
Define the payload power management architecture, including power modes, sequencing, and budgets.
Drive HW, ASIC, and FW/SW embedded integration across the payload.
Lead complex trade-off analyses and drive technical decisions across high-profile, multidisciplinary teams.
Own system requirements throughout the full lifecycle, including design reviews, verification, qualification, and validation.
Design advanced methods and system architectures incorporating array synchronization, calibration, timing distribution, clocking, and related mechanisms to optimize wireless system performance.
Define control procedures, operational flows, and telemetry mechanisms to ensure robust and efficient system performance in the space environment.
Collaborate with world-class R&D teams to create breakthrough technology in an emerging
Support test, qualification, and validation teams, as well as new product introduction for mass production, including optimization of ATE based on characterization and performance analysis.
Support the scaling of service capabilities across multiple constellation generations, optimizing end-to-end ground-to-UE service flows.
דרישות התפקיד
BSc in Electrical Engineering.
5+ years of experience in designing complex HW / ASIC-based systems, including hands-on laboratory testing and integration.
Experience in HW design and ASIC architecture.
Experience in protocols of embedded communication systems (PHY/MAC), including high-speed SerDes interfaces.
Experience in defining system-level software, hardware, and firmware requirements, interfaces, interactions, and flows.
Experience in FW/SW embedded integration with HW and ASIC platforms.