Design Verification Engineer

Company's Profile

CELARE is the Cyber arm of BATM bringing DPI based network perimeter monitoring solutions with integrated Big Data security analytics and threat detection, helping security professionals to better visibility of their networks.

Position summary:

• Ownership of functional verification environment and methodology

• Work closely with all development teams members

Responsibilities:

• Develop verification environments of block level, subsystems and full chip from scratch.

• End to end ownership of the testing process including test plan, agents implementation and coverage collection.

• Develop methodologies, scripts and infrastructure improvements.

• Work closely with RTL & Validation teams.

Requirements:

• BSc/MSc in Computer / Electrical Engineering or equivalent.

• At least 8 years’ experience in RTL design verification

• Knowledge and experience how to bring up an environment from scratch.

• Proficiency with Verilog & System Verilog.

• Proficiency with UVM

• Fluent English

• Strong communication skills, both verbal and written

• Rapid learner, willing to work in dynamic and demanding environment

Location: Petah Tikva