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• Definition, architecture, and development of IP-based block-level verification environments in SystemVerilog, integrated and reused in full-chip environments.
• Building reference models, verification and simulation of SOC modules according to specifications, including performance calculations.
• Working in a combined design and verification team which develops the SOC silicon core units.
• Working closely with multiple teams within the organization, such as Architecture, Software, and Hardware.
  
  

• BSc/MSc in Electrical Engineering or Computer Engineering.
• At least 3 years experience in functional verification. Preferably with SystemVerilog/VMM/UVM.
• Strong debugging, problem solving and analytical skills.
• Team player and fast learner
• Advantage for experience with design, synthesis and post-silicon validation flows.