At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

System VIP (Verification IP) group focuses on developing software for SoC level verification and analysis.

Our System Verification Scoreboard (SVD) is a tool that monitors all the traffic in the system. It provides data, data paths and performance related information to other System-VIP tools, it verifies that all the transactions transmitted and received correctly and according to the design configuration, and that coherency is preserved. SVD is currently focuses on ARM/RISCV/Proprietary interconnects, memory sub-systems and peripherals for typical System-on Chip (SoC), and it works in both Simulation and Emulation verification environments.

The work in System VIP group requires excellent software development skills, self-learning abilities and accountability. It combines interesting and intensive work with customers who are typically industry experts, working with multiple software development languages and multiple technologies.

Managing the SVD development involves leading a team of engineers who are domain experts, interacting with customers around the world, working closely with solution engineer and with other development teams in Cadence.

Job Description

• Leading the development of Cadence System Verification Scoreboard – the most advanced system-monitor in the market
• Implementation of new features with focus on cutting edge designs and features, and communication protocols
• Tight cooperation with multiple teams
• Working with industry leaders’ customers
  
  

• 5-10 years of hands-on experience in software-development or design-verification
• 3-5 years of experience as R&D manager
• Proven experience of managing development team and driving projects with multiple interfaces
• BSc in Computer Science or similar
• Excellent English level
• “Can-Do” attitude
  
  

• Experience in hardware verification
• Knowledge and experience in coherent designs, coherent CHI and ACE, and ARM architectures
• Knowledge in following standard protocol families: AMBA, DDR, PCIE/CXL
• Experience in C++