Software Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

AVIP Group are developing verification components for common and complex protocols, to be used for emulation and simulation.

These products include SystemVerilog/Verilog components and SW components written in C/C++, SystemC, e and SV-UVM.

The development is both on the protocol/product level and the infrastructure level.

Job Description

We are seeking a skilled HW and/or Software Engineer to develop, support and maintain a product for emulation, for common communication protocols.

This job includes full ownership of a product, starting at the definition phase, developing and delivering to the customer.

Cooperating with different teams within Cadence – Development, Marketing, Field, etc. and also with our customers.

Requirements

• BSc in Electrical Engineering from a leading institute
• 1-3 years of hands-on HW development experience in an industrial setting
• Knowledge and experience in Verilog/SystemVerilog.
• Well versed in object-oriented design, SystemC/C/C++ programming experience is a plus
• Good communication skills, excellent inter-personal skills, motivated individual
• Ability to analyze and propose solutions to complex problems.
  
  

• Emulation experience on Palladium
• Familiarity with different communication protocols.
• Familiarity with UVM methodologies.
• Familiarity with Compilation flows and scripting.
• Experience with EDA software.
• Fluent in English