Senior Digital Verification Engineer (CIS)

•    Responsible for the full life cycle of verification, from verification planning to test execution and coverage closure.
•    Plan the verification of complex digital designs from block level up to system level, by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
•    Debug tests with design engineers to deliver functionally correct blocks and finalize regressions.
•     Collaborate closely with all groups in active projects including Design, Algorithm, FW and Analog engineers.
דרישות התפקיד
•    BSc. in Electronic Engineering
•    Minimum 5 years’ experience as a verification engineer, completing at least one chip development cycle.
•    Developed verification environments
•    Knowledge in verification methodologies and tools
•     Knowledge of System Verilog UVM
•    Scripting languages knowledge (perl, python)
•    Methodological approach to the verification tasks planning and execution