ASIC Design Verification Engineer

• UVM environment architecture: Design, build, optimize, and maintain scalable and reusable UVM environments.
• Reference model integration: Integrate and support high-level bit-accurate reference models in C++ to serve as golden references in UVM environments.
• Modern verification techniques: Deploy advanced methodologies including Assertion-Based Verification (SVA), Coverage-Driven Verification (CDV), and formal property checking.
• Automation & Tool creation: Develop internal tools, scripting infrastructure, CI/CD and regression flows (GitLab CI).
• Drive verification efforts across the team.
• Methodology & Sign-off: Review verification plans and establish infrastructure metrics (functional coverage, code coverage, and formal proofs) to drive verification closure.
דרישות התפקיד
• Engineering degree with 15+ years of hands-on experience in ASIC verification using UVM SystemVerilog.
• Experience with UVM, constrained-random verification, and Assertion-Based Verification (ABV).
• Experience with modern EDA tools suites: Questa, Xcelium.
• Experience in unit-level, subsystem, and full-chip verification.
• Experience working on complex ASIC or SoC designs.
• Strong proficiency in Python, SCons, Makefile, and Git for automation flows, regression management, and data parsing.
• Good knowledge of C/C++ is a plus.
• Strong system-level understanding.
• Experience with SoCs in the communications field – advantage.