Logic Digital Verification Engineer JB-2946

The company is looking for a talented and experienced engineer to take part in the verification efforts for the company’s core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.

In Addition, it involves day to day work with other groups within the company such as System, Software, Analog, DFT and LAB activity according to needs

Responsibilities

Work with Designers and architects defining verification methodologies

Build and maintain an agile verification environment that ties into various systems (MATLAB, SW stack, FPGA, HW/SW Co-simulation and Verilog-HDL)

Work closely with the software, design, Analog, and System teams to understand the functional, Power and performance goals of the product’s and ensure the quality of the product

Review specifications and develop attributes, tests, and coverage plans

Define methodologies and test benches

Maintain Linux environment and release flow involving several R&D groups including version control (GIT) and internal developed tools Requirements

Requirements:

5+ years of System Verilog UVM DV experience.

Knowledge of Python, shell scripting.

Knowledge of assertions (SVA) or others.

Knowledge of digital ASICs design flows.

Knowledge of industry-standard tools, including Verilog, Verilog simulator, and debug

Bachelor’s or Master’s degree in electrical engineering or computer science, or equivalent experience

Functional Verification - System Verilog, Universal Verification Methodology (UVM)

Verilog, Application-Specific Integrated Circuits (ASIC)

Unix, Scripting - Python, Make, C-Shell/Bash

Version control (GIT)

SoC development work methodologies and tools