Verification Engineer

We are looking for Verification Engineer for our team in Elbit Systems Holon

+3 years of experience in verification flow, from Test Plan definition to Coverage

Developing Verification environment base UVM-SV for diverse projects as signal processing, controllers and more

Definition and implementation verification environment from Block level to Full-chip

Working closely with FPGA designers, architecture/system engineer and algorithms



B.Sc in Electrical or Computer Engineering

Experience with UVM methodology and System Verilog

Experience with RTL debugging from block level to System level

Experience with simulation tools Questa Simulator – an advantage

Scripting and programming experience using several of the following: TCL, Python, csh/bach

Experience with Linux an NC