At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an exceptionally talented IP layout lead. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. This role is for an analog layout IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production.

Description

Senior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. As a member of the AMS layout team you will be responsible to deliver Physical Design Verification clean layout, this includes the following: Crafting complex layout for mixed signal, and analog circuits in deep SubMicron CMOS technologies. Reviewing and analyzing floor-plans and complex circuits with circuit designers. Running complete set of design verification tools available on AMS blocks. Working with the circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed. Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. Exceeding engineering specifications and expectations by working closely with the circuit design team. Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.

Key Qualifications

10+ years of experience in analog/mixed-signal layout design of deep sub micron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFet technologies.
Experience crafting tight matching, low noise, and low power analog blocks, resistors, capacitors, pad IO's, ESD structures, etc.
High level of proficiency in custom and standard cell based floor-planning and hierarchical layout assembly.
Must understand issues of IR drop, RC delay, electro-migration, self heating and cross capacitance.
Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer for the best approach to problems.
High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., reports.
Knowledge of MENTOR GRAPHICS or CADENCE layout tools.
Scripting skills in Perl, Python or SKILL an advantage.
Excellent interpersonal skills and ability to work with multi-functional teams.

Education & Experience

Excellent EE Practical Engineers or Bachelors of Science (preferred)

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