SoC Design Engineer, Hardware, Google Cloud

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• Experience in ASIC development with Verilog/SystemVerilog, VHDL.
• Experience in logic design and debug.
• Experience with ASIC design verification, synthesis or timing/power analysis, or DFT.
  
  

Preferred qualifications:

• Domain knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors family.
• Knowledge of high performance and low power design techniques.
• Knowledge of SOC architecture.
• Knowledge of assertion-based formal verification.
• Proficiency with a scripting language like Python or Perl.
  
  

About The Job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

In this role, you will contribute in all phases of complex Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power, and area in mind.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
• Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
• Participate in test plan and coverage analysis of the block and SOC-level verification.
• Communicate and work with multi-disciplined and multi-site teams.
  
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .