Physical Design Engineer, Static Timing Analysis

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience
• Experience in RTL2GDS, STA flows, and methodologies
• Experience with physical design tools (e.g., Synopsys, Cadence) and timing signoff (Primetime)
• Experience with Static Timing Analysis, sign-off corner definitions, process margining, SDC development, high frequency convergence, and setting up frequency goals with technology scaling
  
  

Preferred qualifications:

• Experience with AC timing from specs to implementation
• Experience with CDC design and CDC constraints
• Experience in ASIC physical design, physical design flows and methodologies, synthesis, place and route, and formal verification
• Understanding of DFT modes
• Understanding of noise and signal integrity effects
  
  

About The Job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Work closely with multiple teams like architecture, Logic Design, DFT, and physical design from early stages to define and implement constraints for the various modes through timing convergence to full signoff.
• Define overall Static Timing Analysis (STA) methodology, STA infrastructure, and sign-off convergence flows.
  
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .