Senior Physical Design Engineer

•    Execute the full Place & Route (P&R) flow at both hierarchical and top levels, from netlist to GDSII.
•    Perform placement, clock tree synthesis, routing, STA, and physical verification (DRC, LVS, ANT, etc.).
•    Ensure timing closure and design convergence across multiple stages of implementation.
•    Collaborate closely with front-end, architecture, and verification teams to achieve best-in-class design quality and performance.
•    Drive design improvements and maintain methodologies for backend flow efficiency.
דרישות התפקיד
•    B.Sc. in Electrical Engineering from a recognized university.
•    6+ years of hands-on experience in automatic Place & Route (block level and top level).
•    Strong scripting skills in TCL.
•    Proven ability to work effectively in a multi-disciplinary and multi-site environment.
Advantages
•    Familiarity with circuit optimization, IR drop, and EM prevention considerations.
•    Experience with Cadence P&R tools and flows.
•    Knowledge of advanced technology nodes (16nm and below).