CAD PDV Junior Engineer

Summary

Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, across the whole portfolio, from full custom analog to multi die system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices.

As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and runset development for various technology nodes and tool sets. Working alongside the CAD team, you will have the opportunity to learn and collaborate with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have experience with design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Knowledge with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules is a plus.

Key Qualifications

+ 3 years of relevant industry experience.

Previous industry experience in Silicon chip design flows

Knowledge in Calibre/ICV runset coding for DRC/LVS/ERC/MFILL is required

Tapeout support and chip level PDV debug experience is a plus

Knowledge/scripting in programming languages such as Perl, Python, Tcl, Shell, Makefile or C.

Understanding in Silicon technology and experience with flow development in advanced nodes

Description

•Improve and maintain physical verification flows and methodology

•Collaborate with team members on flow automation and data generation

•Install and support foundry PDV collateral for various technologies

•Create in-house PDV rule decks for custom designs

•Facilitate chip design process by debugging layout/schematic issues in custom IPs

Education & Experience

BS electrical engineering

Role Number: 200515671