Senior Design Verification Engineer

Responsibilities:

• Mastering complex designs and applications in the field of deep learning in close collaboration with HW team.
• Take part in all aspects of digital design verification – from specifications, test plan, execution, debug and coverage, in block-level to chip-level environments.
• Investigate, develop and work with advanced verification methodologies implementing state-of-the-art methods.
• Close collaboration with design, software and algorithms teams in debug, SW bring-up and developing shared resources.

Requirements:

• B.Sc. in Electrical or Computer Engineering/Computer science.
• At least 3 years experience in the Verification flow of complex designs from test plan definition to coverage closure
• Experience in Specman – an advantage
• Experience in UVM – an advantage
• Experience in Formal Verification – an advantage
• Background in processors architecture and principles - advantage
• Background in deep learning, computer vision, communication or DSP – advantage

Personal skills:

• Team player with proactive attitude
• Thinker, self-learning, curious and motivated

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