The Senior FPGA Design Engineer will be responsible for high reliable real-time FPGA logic development

Key Qualifications

• Proficient in Verilog RTL language. Experienced with large FPGA development on Xilinx devices.
• Very familiar with Xilinx's build flow including design entry in Verilog, synthesis, place and route, timing constraints and timing closure.
• Hands on with lab FPGA debug methodologies.
• Hands on experience with lab debug equipment, such as oscilloscopes and logic analysers.
• Experience with verification methodologies, RTL and gate level simulations and debug.
• Experience debugging silicon and PCB issues.
• Excellent communication skills and demonstrate the desire to take on diverse challenges.
• Run basic verification tests (on simulations)
• on target integration and testing

Advantages

• ASIC Design/Verification experience
• Able to write scripts in python, Perl or other scripting languages
• Experience and strong foundations in digital design and communications.
• Beamforming knowledge
• Education & Experience
• BSc/ MSc in Electrical Engineering
• 5 or more years of experience developing FPGA or ASIC systems.

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