Verification Engineer

Looking for a talented Digital Verification Engineer for a global hi-tech company in Tel Aviv!

What will you do?

• Responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.
• Plan the verification of complex design blocks by fully understanding the design specification, working closely with architecture, design, algorithm teams.
• Leading the top-level IP verification effort from planning to delivery.
• Create a constrained-random verification environment using SystemVerilog and UVM.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Collaborate closely with design and verification engineers in active projects and perform hands-on verification.

Qualifications:

• BSc. in Electronic Engineering MSc. an advantage
• At least 3 years’ experience as verification engineer. Completing full development cycle an advantage.
• Knowledge in verification methodologies, tools (simulators, coverage tools, etc.), and techniques
• Knowledge of Verilog, System Verilog or Specman
• Developing UVM based verification environments
• Developing UVM based verification environments
• Experience in Python / Perl programming
• Good knowledge of UNIX environment