CPU Design Integration Lead, Google Cloud

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
• Experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language.
• Experience with chip design flow, physical design, IP integration, DFT.
  
  

Preferred qualifications:

• Master's degree or PhD in Engineering.
• Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
• Experience in leading chip development projects or teams.
• Ability to motivate and focus a large collaboration to reach challenging goals.
• Excellent communication and facilitation skills.
  
  

About The Job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Define and drive the RTL changes required for physical reference design, coding of memories, coding of partitions, SCAN insertion and MBIST definition, external IPs insertion per the SOC definition (thermal sensors, aging IPs, etc).
• Drive the process and delivery of a basic physical reference design, definition of partitions, floor plan, library and IPs selection, DFT integration, etc.
• Own all aspects of IP readiness for SOC integration and coordination with the SOC owners.
• Resolve complex technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures.
• Be responsible for project development with the highest Quality, deal with issues as they arise through design and implementation.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .