Full Chip Timing Lead

Which department will you join?

Mobileye EyeC VLSI team - a group designing the chips for RADAR and LiDAR systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.

We’re looking for a Full Chip Timing Lead to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.

What will your job look like:

• Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
• Writing design constraints (SDC) for FC/IP/Block levels for all modes.
• Involved in chip architecture definition for functional & DFT domains.
• Working in close collaboration with the front-end & architecture team.
• Working with engineers to identify and overcome roadblocks and obstacles.
• Defining AC timing from spec to implementation.
• Supporting complex clock structures.
  
  

• BSc/MSc in Electrical Engineering/Computer Science.
• STA Expert (Prime-Time/Signoff).
• 8 years of experience in VLSI backend (RTL2GDS).
• 5 years of experience in full chip STA on complex SoCs.
• Expert knowledge in timing closure & signoff methodologies.
• Experience with DFT architecture, Async timing concepts & verification.
• Experience in technically leading complex backend activities, preferably of complete SoC's.
• Expert knowledge of the entire backend design flow from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration, high-frequency designs).